1. Field of the Invention
The present invention relates to a semiconductor apparatus. More particularly, the present invention relates to a semiconductor apparatus for reliable analysis of signals.
2. Description of the Related Art
A semiconductor apparatus often carries out data analysis or comparison of signals. In particular, a semiconductor apparatus for testing a semiconductor circuit compares a circuit response signal from the semiconductor circuit with an expected response signal expected to be sent from the semiconductor circuit.
A data analyzer is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 6-201801). The conventional data analyzer includes exclusive-OR gates 101-104 and an OR gate 105, as shown in FIG. 1. First inputs of the exclusive-OR gates 101-104 are coupled to receive a circuit response signal (CIRCUIT RESPONSE (X)), respectively. CIRCUIT RESPONSE (X) is the signal outputted by the semiconductor circuit to be tested. Second inputs of the exclusive-OR gates 101 to 104 are coupled to receive an expected response signal (EXPECTED RESPONSE (X)), respectively. EXPECTED RESPONSE (X) is the signal expected to be outputted by the semiconductor circuit. Each of the exclusive-OR gates 101 to 104, if CIRCUIT RESPONSE (X) and EXPECTED RESPONSE (X) coincide with each other, outputs “0”, and if they do not coincide, outputs “1”. Respective outputs of the exclusive-OR gates 101 to 104 are connected to respective inputs of the OR gate 105. An output of the OR gate 105 is connected to a terminal 106. On the basis of a signal appearing in the terminal 106, it is judged whether or not CIRCUIT RESPONSE (X) and EXPECTED RESPONSE (X) coincide with each other.
However, the conventional data analyzer can not distinguish a case when the data analyzer has a failure from a case when the tested semiconductor circuit has a failure. For example, let us suppose that the exclusive-OR gate 101 has a failure and the output of the exclusive-OR gate 101 is fixed to a logic “0”. In this case, it can not be judged from the signal outputted by the exclusive-OR gate 101 whether the exclusive-OR gate 101 outputs the logic “0” since signal CIRSUIT RESPONSE (0) and EXPECTED RESPONSE (0) coincide with each other, or the exclusive-OR gate 101 outputs the logic “0” since the exclusive-OR gate 101 has a failure and the output of the exclusive-OR gate 101 is fixed to the logic “0”.
Other techniques for testing circuits are disclosed in Japanese Laid Open Patent Application (Jp-A-Heisei 10-187554, Jp-A 2000 76894). However, none of the disclosed techniques deals with the above-mentioned problem.
Still another technique for self-testing of a circuit is disclosed in Japanese Patent Gazette (Jp-B-Heisei 7-31610). However, the disclosed circuit do not achieve a reliable self-test if the testing circuit has a failure and thereby the output of the testing circuit is fixed to a value.
It is desired to eliminate the possibility that compared signals are recognized to be identical because of a failure of a comparing circuit.